1. Field of the Invention
The invention relates to methods of making integrated circuits. More specifically it relates to methods of fabricating interconnect structures in semiconductor devices.
2. Description of Related Art
The need for lower resistance and capacitance in interconnect dielectric films caused by the ever-increasing miniaturization of semiconductor devices has led to the use of copper to form interconnects and vias rather than aluminum. When those structures are formed from copper a dual damascene process is typically used, in view of the difficulty in dry etching copper.
Dual damascene processes are loosely classified into trench first and via first types, each of which includes a variety of subtypes. For example, U.S. Pat. No. 6,083,824 discloses patterning a hard mask to define a trench pattern to be formed in an underlying interlayer dielectric, and then forming a photoresist layer bearing a via hole pattern overlapping the hard mask, to improve alignment of the trenches and vias. The vias are etched through the photoresist and the hard mask, and following removal of the photoresist the trenches are formed through the hard mask.
However, as chip sizes and circuit layouts continue to shrink, the aspect ratio of the layers utilized to form the interconnect structures increases, and in particular increasingly thick hard masks are needed. Moreover, in trench first techniques where the hard mask bearing the trench pattern is used also to align the vias, the mask is often exposed to two etching steps. Such processes are therefore limited in that, even with increased hard mask thickness and selection of dielectric etch chemistries for via formation that are selective against the metal hard mask, the hard mask layer is increasingly eroded. Moreover, the need for thicker mask layers unnecessarily increases the aspect ratio of overlying layers, which can lead to pattern collapse of the intermediate structures.